1. Field of the Invention
The invention relates to the field of microelectronics fabrications. More specifically, the invention relates to methods for forming patterned dielectric and conductor layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications employ various layers of microelectronics conductor, semiconductor and dielectric materials formed into patterns on substrates in order to build up the constituent portions of the fabrication. When multiple layers of patterned conductors are insulated from each other employing dielectric layers, it is desirable to reduce capacitance between conductor layers and between lines within a patterned conductor layer to optimize circuit speed and performance. Hence the employment of low dielectric constant (low-k) dielectric materials to form the insulator layers has become increasingly common.
Among the low dielectric constant dielectric materials available to form dielectric layers between conductors, especially desirable are the fluorine doped silicon containing glass (FSG) dielectric layers formed employing chemical vapor deposition (CVD), and organic polymer materials such as, for example, fluorinated poly (arylene ether) spin-on-polymer (SOP) dielectric materials. It is often necessary to form via contacts through such low-k layers and to form conductor patterns inlaid within trenches formed within such low-k layers by subtractive etching. Such patterned conductor layers afford a maximum amount of low dielectric constant dielectric material around the conductor lines. The etching methods employed are oxidizing and related plasmas which are often destructive of organic polymer photoresist etch mask layer materials conventionally employed, and require a non-reactive hard mask cap layer formed over the low-k layer as an etch mask layer. Typically such hard mask layers are formed of silicon containing dielectric materials such as silicon nitride employing methods such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD) and atmospheric pressure chemical vapor deposition (APCVD).
While generally satisfactory as etching mask layers, such silicon containing hard mask layers are not without problems. In particular, the adhesion of layers of silicon containing dielectric materials to underlying layers of low-k dielectric materials may be marginal with respect to withstanding subsequent processing procedures employed after subtractive etching without delamination.
It is often of practical use to be able to form patterns in layers formed upon substrates which can then be subsequently delaminated by simple processing. The removal of a second layer overlying the patterned layer can then be effected when the patterned layer is detached from the substrate by the process, leaving behind the reverse of pattern of the second layer on the substrate. The principle may be employed to form patterns in microelectronics fabrications of material layers which are difficult to etch subtractively employing conventional methods.
It is thus towards the goal of employing low dielectric constant dielectric material in methods to form patterned conductor layers having maximized the amount of low dielectric constant dielectric layer around the conductor layers within microelectronics fabrications that the present invention is directed.
Various methods have been disclosed for forming patterned low dielectric constant dielectric layers and conductor layers employing hard mask cap layers within microelectronics fabrications.
For example, Havemann, in U.S. Pat. No. 5,482,894, discloses a method for forming a narrow aperture width high aspect ratio self-aligned contact via hole to access contact layer in an organic dielectric layer between patterned conductor layers employing a silicon oxide cap layer as an etching mask. The completed inter-level metal dielectric (IMD) layer is comprised of the organic dielectric layer and the intact remaining hard mask silicon oxide dielectric layer.
Further, Havemann et al., in U.S. Pat. No. 5,488,015, disclose a method for forming a low dielectric constant dielectric layer with reduced capacitance between adjacent conductors employing a porous dielectric material overlaid with a second non-porous dielectric cap layer. The porosity of the low dielectric constant dielectric underlayer is a function of its preparation from a precursor gel layer, and is protected by the cap layer formed of a non-porous material such as silicon oxide.
Still further, Lou et al., in U.S. Pat. 5,759,906, disclose a method for forming a an inter-level metal dielectric (IMD) layer employing PECVD silicon oxide layer and a low dielectric constant dielectric layer to provide reduced capacitance and RC time delay. The low dielectric constant dielectric layer is formed of multiple layers of spin-on-glass (SOG) or spin-on-polymer (SOP) dielectric materials. A cap layer of silicon oxide dielectric material, undoped or fluorine-doped, is formed over the low dielectric constant layer which permits planarization by chemical mechanical polish (CMP) planarization.
Finally, Chen et al., in U. S. Pat. No. 5,858,869, disclose a method for forming an inter-level metal dielectric (IMD) layer with low dielectric constant. The method employs an anisotropic silicon oxide layer formed over and along conductor lines, followed by a low dielectric constant polymer dielectric layer. After planarization polishing back to the top of the conductor lines, a fluorine doped silicon containing glass (FSG) layer is formed over the surface and via holes etched to complete the IMD layer.
Desirable in the field of microelectronics fabrication are additional methods employing hard mask cap layers for forming patterned low dielectric constant dielectric layers and conductor layers.
It is towards this goal that the present invention is generally and more specifically directed.
A first object of the present invention is to provide a method for forming a patterned conductor layer within a low dielectric constant dielectric layer upon a substrate employed within a microelectronics fabrication wherein the amount of low dielectric constant dielectric material is maximized around the patterned conductor layer.
A second object of the present invention is to provide a method in accord with the first method of the present invention, where the patterned low dielectric constant dielectric layer forms an inter-level metal dielectric (IMD) layer.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a patterned conductor layer employing a patterned hard mask cap layer to practice the invention, there is first provided a substrate having within it patterned conductor regions over which is formed a low dielectric constant dielectric layer etchable in a plasma. Formed over the low dielectric constant dielectric layer is a blanket silicon containing hard mask cap layer. There is then formed over the hard mask cap layer a patterned photoresist etch mask layer. There is then subtractively etched employing the patterned photoresist etch mask layer and a first etching environment the pattern through the hard mask layer, and then employing the hard mask layer as an etch mask and a second etching environment the pattern into the low dielectric constant dielectric layer. If the latter etching environment is an oxygen containing or oxidizing plasma, it may be simultaneously employed to strip the photoresist etch mask layer. Employing a suitable chemical treatment, the hard mask layer is then delaminated from the low dielectric constant dielectric layer, leaving an etched trench pattern within the dielectric layer. The pattern in the low dielectric constant dielectric layer is then filled with a microelectronics material to form an inlaid pattern. The order of filling and delamination of the hard mask layer may be reversed if it is desired to minimize the amount of excess material remaining on the substrate after filling the trench pattern in the dielectric material. The excess material may then be removed and the surface planarized by chemical mechanical polish (CMP) planarization to provide a co-planar surface. Subsequently, an upper patterned conductor layer may be formed over the substrate to complete an inter-level metal dielectric (IMD) layer with,maximized amount of low dielectric constant dielectric material around the patterned conductor layer.
The present invention provides a method for forming within a low dielectric constant dielectric layer formed over a substrate employing a patterned hard mask layer a patterned microelectronics layer which may be employed as a via contact stud layer or part of an inlaid conductor interconnection layer within an inter-level metal dielectric (IMD) layer. The present invention provides a method to maximize the amount of low dielectric constant dielectric material around the patterned microelectronics layer employed with an inter-metal dielectric (IMD) layer.
The present invention employs methods and materials which are known in the art of microelectronics fabrications, but in a novel order and sequence. The method of the present invention is therefore readily commercially implemented.